Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device in which bit lines are hierarchically structured.
Description of Related Art
In some of semiconductor devices represented by a DRAM (Dynamic Random Access Memory), bits lines are hierarchically structured into local bit lines and global bit lines (see Japanese Patent Application Laid-open No. H8-195100 and Japanese Patent Application Laid-open No. 2011-34614). The local bit lines are low-order bit lines and are connected to memory cells. The global bit lines are high-order bit lines and are connected to sense amplifiers. When the bit lines are hierarchically structured, the number of memory cells that are allocated to one sense amplifier can be increased while the wiring length of the local bit lines having relatively-high electrical resistances can be shortened.
However, in the conventional semiconductor device having hierarchically structured bit lines, when a defective word line is to be replaced with a redundant word line, the redundant word line must be selected among redundant word lines that intersect with the same local bit line that intersects the defective word line. That is, the defective word line can be replaced only within a memory sub-mat in which the local bit line extends and thus its relieving efficiency is low.